1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit (IC) memory device with enhanced reliability.
2. Description of the Related Art
Static random access memories (SRAMs) have a smaller memory capacity for a given chip area but a higher operating speed than dynamic random access memories (DRAMs). Accordingly, SRAMs are widely used in cache memories of computers or portable appliances that are required to operate at high speed.
SRAM cells are divided into thin-layer transistor (TFT) cells and full complementary metal oxide semiconductor (FCMOS) cells. An FCMOS cell includes a plurality of cross-connected pull-up transistors and pull-down transistors that constitute a latch and a plurality of pass transistors that access the latch.
As semiconductor memory devices become more highly integrated, memory cells are becoming smaller. As the size of memory cells decreases, the size of metal contacts in them is also decreasing. However, a decrease in the size of the metal contacts makes it difficult to accurately pattern the metal contacts, resulting in an increase in the occurrence of defective contacts. In particular, adjacent ones of shared contacts formed in SRAM cells tend to be easily electrically connected (shorted) to each other, also known as bridged.